It is known in the prior art to provide automatic test equipment ("ATE") to evaluate VLSI chips by sending electrical bursts into certain terminals and comparing resultant terminals outputs with selected standards.
It is known also to use gallium arsenide chips for ATE analog circuitry (e.g., in drivers and comparators).
It is known to produce, in silicon, driver edge positioning by varying the delay produced in particular timing generators from period to period within a burst.
Further it is known in the silicon prior art to refine delays produced by timing generators by means of verniers given improved accuracy by means of complex and expensive IC circuitry, sometimes including additional correction circuits.
It is further known in the prior silicon ATE art to provide elaborate calibration circuits internal to an IC such that an edge delay desired at the DUT terminal is linearly directly responsive to a command at the computer, colinearly for each channel.
Finally, it is known. in the silicon ATE art to produce DUT terminal edges at selected delays of greater length than a period, by using extra (e.g., "even/odd") timing generators.